Korean Institute of Surface Engineering

pISSN : 1225-8024 | eISSN : 3399-8403


공학

한국표면공학회지 (54권5호 207-212)

FE-SEM Image Analysis of Junction Interface of Cu Direct Bonding for Semiconductor 3D Chip Stacking


Jaeduk Byun, June Won Hyun*


Department of Physics, Dankook University, Dandae-ro, Dongnam-gu, Cheonan-si, Chungnam, 31116, Korea

DOI : 10.5695/JKISE.2021.54.5.207

Abstract

The mechanical and electrical characteristics can be improved in 3D stacked IC technology which can accomplish the ultra-high integration by stacking more semiconductor chips within the limited package area through the Cu direct bonding method minimizing the performance degradation to the bonding surface to the inorganic compound or the oxide film etc. The surface was treated in a ultrasonic washer using a diamond abrasive to remove other component substances from the prepared cast plate substrate surface. FE-SEM was used to analyze the bonding characteristics of the bonded copper substrates, and the cross section of the bonded Cu conjugates at the sintering junction temperature of 100 °C, 150 °C, 200 °C, 350 °C and the pressure of 2303 N/cm2 and 3087 N/cm2. At 2303 N/cm2, the good bonding of copper substrate was confirmed at 350 °C, and at the increased pressure of 3087 N/cm2, the bonding condition of Cu was confirmed at low temperature junction temperature of 200 °C. However, the recrystallization of Cu particles was observed due to increased pressure of 3087 N/cm2 and diffusion of Cu atoms at high temperature of 350 °C, which can lead to degradation in semiconductor manufacturing.

Keywords

Semiconductors, 3D chip stacking , Cu direct bonding, Interface